This invention relates to a circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, and more particularly, relates to a circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, which device comprises at least one differential cell multiplier whose cell includes a pair of input MOS transistors having respective conduction terminals linked together at a circuit node.
As is well known, disk units are commonly employed in computers for storing and reading data. Disk drive units conventionally comprise stacked magnetic hard disks which can be set in rotary motion. Data is stored onto these disks in a magnetic format, and data is written to and read from these disks by means of magnetoresistive heads.
The data is recorded in radially concentric tracks which are spaced apart across a surface of each magnetic disk. The magnetoresistive heads are steered along predetermined paths to and from the disk surface for the purpose of reading or writing data.
To obtain high storage densities and a large proportion of data for read/write processing, sampling and sensing techniques are used with PRML (Partial Response signalingxe2x80x94Maximum Likelihood) channels.
For example, a sequential PRML sensing technique is used conventionally in applications relating to digital data communication and recording, as described in U.S. Pat. No. 4,786,890.
To fully benefit from the advantages of the PRML technique, a received or sense signal is to go through an appropriate equalizing filter which will output a signal spectrum corresponding to the waveform for which the maximum-likelihood detector has been designed.
Where a digital filter is used in a PRML system, the filter is usually placed between an analog/digital converter (ADC) and other circuitry arranged to control the system and execute the sensing operation.
Unfortunately, conventional read channels often experience problems connected with data processing rate and power requirements of the operation.
With recent PRML channels and magnetoresistive heads, the output signal from a head shows asymmetries of amplitude in the positive and negative signals, which asymmetries depend on the point of static bias of the head and on flight altitude during the transfer phases.
FIG. 1 of the accompanying drawings shows schematically a graph wherein the symmetric response of the channel is plotted on the abscissa axis and the variation in resistance of the head plotted on the ordinate axis. It can be evinced from this graph that the waveform of the signal departs from a true parabola at opposed ends. Such departures are due to demagnetization fields.
Before a signal such as this is subjected to analog/digital conversion for the purpose of processing the data in the digital format, it is expedient to rectify the asymmetries by normalizing the read signal with an amplification, e.g., by means of a VGA (Variable Gain Amplifier). In fact, it is preferable to operate at constant amplitude after the signal is filtered through a loop integrator, e.g., of the AGC type, that is after the loop has settled, the AGC loop being effective to settle the peak-to-peak ratio of the signal.
As a preliminary approximation, the asymmetry of a signal is quadratic in nature, and the response g(t) from an asymmetric channel is given as:
g(t)=h(t)xe2x88x92Casymmh(t)2 
where, h(t) is the response from the symmetric channel.
Assuming the maximum value of h(t) to be 1, then the amplitude ratio of the positive and negative peaks will be the value of the asymmetry.
FIG. 2 is a schematic block diagram of a resolutive circuit according to the prior art, intended to restore the symmetry of an output signal from a read head. The block is generally referenced 1.
The signal xMR(t) from the VGA is input to a multiplier block 2, which block is usually in the form a feedforward type of four-quadrant multiplier.
The output signal from the block 2 is applied to an amplifier 3 having an amplification parameter xcex1.
This amplifier 3 receives, from a five-bit digital/analog converter 4, a signal MRA representing an amplitude asymmetry sensed by a read head.
The amplifier 3 outputs a signal xMRAC(t) which is then applied to a summing node 5.
The summing node 5 also receives the original signal xMR(t) through a delay block 6 which is only operative to equalize the delays, so that the same phase relation can be had at the output.
Thus, the sum carried out in the summing node 5 will result in a signal xOUT(t) being output to a low-pass filter.
The relations on which the operation of the above prior solution is based will now be reviewed.
The input signal is raised to the second power and amplified by the parameter xcex1 in the first leg, and is only retarded through the second leg. The outcome of these operations is:
xMR(t)=x(t)+xcex1*x2(t) 
The signal xMRAC(t) is expressed by the following relation:
xMRAC(t)=xcex1xe2x80x2(x2(t)+2xcex1*x3(t)+xcex12*x4(t)); 
where, xcex1xe2x80x2 approximately equals xcex1, since the terms of the second order may be neglected.
It follows from the above that the value of the output signal xOUT(t) can be calculated as:
xOUT(t)=xMR(t)xe2x88x92xMRAC(t)=x(t)+xcex1*x2(t)xe2x88x92xcex1xe2x80x2(x2(t)+2xcex1*x3(t)+xcex12*x4(t)); 
whence:
xOUT(t)=x(t). 
While being in several ways advantageous, this prior solution only enables positive or negative asymmetries to be suppressed, at the expense of enhanced circuit complexity and power consumption.
Furthermore, for the multiplier block, a Gilbert""s CMOS multiplier with four quadrants is usually employed which is slow and not so accurate.
The underlying technical problem is to provide a circuit device for restoring the symmetry of the analog signal output from a read head for reading data stored in magnetic supports, which device has such structural and functional features as to altogether suppress asymmetries by means of a circuit structure that is uniquely simple and effective, thereby overcoming the limitations of prior art solutions.
The principle on which the disclosed embodiment of this invention stands is one of using a multiplication cell with variable transconductance, which cell has a pair of input transistors associated with a plurality of transistors selectively connectable in parallel with each of said input transistors by means of corresponding switches.
Based on this principle, the technical problem is solved by a device as previously indicated that provides in parallel with each of the cell input transistors a plurality of transistors that are selectively connectable individually to each of the input transistors by corresponding switches.
Advantageously, each transistor of said plurality is connected in series with a respective current generator, between a supply voltage (vcc) and ground, and a conduction terminal of each transistor is connected to said node by a respective switch.